The subject matter disclosed herein relates to integrated circuit (IC) wafer structures and methods for identifying the location of a particular die after dicing of the wafer. More specifically, aspects of the invention relate to structures which include identification features for indicating the original location of a circuit die on an IC wafer, methods of forming such features, and methods of using such features.
Integrated circuit manufacturing includes fabricating the structure of multiple circuit dies together on a single semiconductor wafer. After forming one semiconductor wafer, the wafer may be split into multiple circuit dies. Wafer dicing refers to the process of dicing (i.e., splitting) the single semiconductor wafer into a plurality of circuit dies for conversion into end products. The dicing of a wafer includes defining a set of scribe lines, alternatively known as kerf lines, for separating various regions of the wafer, such that each region includes the structure of a particular die bounded by a corresponding set of scribe lines. The dicing process may include the mechanical splitting of the wafer, e.g., by laser cutting and/or other procedures for separating semiconductor material and elements formed therein into smaller pieces.
One underlying characteristic of wafer dicing is the loss of materials included at or near the set of scribe lines. These materials and regions may be known as the IC wafer's kerf region. Conventional testing methods may include forming various structures, features, etc., in the kerf region of an IC wafer to determine the quality of a wafer before it is diced. IC wafers that pass this stage of testing will then be diced, and the test structures included in the kerf regions of the wafer will be removed or otherwise disconnected from functional components of the individual circuit dies. Pre-dice testing of an IC wafer may not fully account for post-deployment characteristics of a particular product, e.g., functional failures of a fabricated unit. After a wafer is diced, the various wafer dies may be intermixed and/or distributed to different customers or sites without regard to which wafer, or portion of a wafer, may have been used to produce each circuit die. Conventional testing may be limited to evaluating the characteristics of the entire wafer prior to dicing, or examination of particular units after manufacture, without any ability to associate an end product or batch of products with a particular portion of the original wafer.